package CPU.rv64_1stage

import difftest._
import chisel3._

class SimTop extends Module {
  val io = IO(new Bundle{
    val logCtrl = new LogCtrlIO
    val perfInfo = new PerfInfoIO
    val uart = new UARTIO
    val a = Input(UInt(4.W))
    val b = Output(UInt(4.W))
  })
  io.logCtrl  := DontCare
  io.perfInfo := DontCare
  io.uart     := DontCare
  val difftest = Module(new DifftestInstrCommit)
  difftest.io := DontCare
  io.b := io.a + 1
//  lazy val config = NutCoreConfig(FPGAPlatform = false)
//  val soc = Module(new NutShell()(config))
//  val mem = Module(new AXI4RAM(memByte = 128 * 1024 * 1024, useBlackBox = true))
//  // Be careful with the commit checking of emu.
//  // A large delay will make emu incorrectly report getting stuck.
//  val memdelay = Module(new AXI4Delayer(0))
//  val mmio = Module(new SimMMIO)
//
//  soc.io.frontend <> mmio.io.dma
//
//  memdelay.io.in <> soc.io.mem
//  mem.io.in <> memdelay.io.out
//
//  mmio.io.rw <> soc.io.mmio
//
//  soc.io.meip := mmio.io.meip
//
//  val log_begin, log_end, log_level = WireInit(0.U(64.W))
//  log_begin := io.logCtrl.log_begin
//  log_end := io.logCtrl.log_end
//  log_level := io.logCtrl.log_level
//
//  assert(log_begin <= log_end)
//  BoringUtils.addSource((GTimer() >= log_begin) && (GTimer() < log_end), "DISPLAY_ENABLE")
//
//  // make BoringUtils not report boring exception when EnableDebug is set to false
//  val dummyWire = WireInit(false.B)
//  BoringUtils.addSink(dummyWire, "DISPLAY_ENABLE")
//
//  io.uart <> mmio.io.uart
}

object u_simtop {
//  implicit val sodor_conf = SodorConfiguration()
  def main(args: Array[String]): Unit = {
    chisel3.Driver.execute(args, () => new SimTop())
  }
}